The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device and a method of fabricating the same, by which high-speed operations and high integration can be realized in a DRAM (Dynamic Random Access Memory) or in an embedded device having both a DRAM and a logic circuit.
A trench capacitor and a stacked capacitor are currently most popular as a storage node of a DRAM. In particular, a trench capacitor is often used as a capacitor suited to an embedded device for the following reasons. That is, since the capacitor can be formed before the formation of a logic circuit, the logic process is less influenced. In addition, the capacitor is buried in a silicon substrate, so no such deep contact formation as for a stacked capacitor is necessary in an interconnection step.
The structure of a trench capacitor relevant to the present invention will be described below with reference to its fabrication method.
FIGS. 19A to 20C are sectional views showing the steps of the method of fabricating the trench capacitor related to the present invention.
First, as shown in FIG. 19A, a 5-nm thick silicon oxide film 102 and a 150-nm thick silicon nitride film 103 are deposited on a silicon substrate 101. A photoresist 104 is removed by photolithography from a region where a trench is to be formed. The silicon oxide film 102 and the silicon nitride film 103 are etched away by RIE (Reactive Ion Etching).
As shown in FIG. 19B, RIE is again used to etch the silicon substrate 101, forming a trench 105 about 5 μm deep from the silicon surface. After that, the photoresist 104 is removed.
As shown in FIG. 19C, a silicon nitride film 106 about 5 nm thick is formed on the inner walls of the trench 105. Additionally, first polysilicon 107 doped with an n-type impurity such as arsenic (As) is deposited to have a thickness of about 500 nm, thereby completely filling the trench 105.
As shown in FIG. 19D, an etch back process using CMP (Chemical Mechanical Polishing) and RIE is performed to etch the surface of the polysilicon 107 to a depth of about 0.5 μm from the surface of the silicon substrate 101. Furthermore, the silicon nitride film 106 exposed to the inner walls of the trench is etched away, and a collar silicon oxide film 108 about 100 nm thick is deposited.
As shown in FIG. 20A, second polysilicon 109 is buried. More specifically, the collar silicon oxide film 108 on the substrate 101 is etched by RIE so as to remain only on the side walls of the trench. In addition, second polysilicon 109 doped with an n-type impurity such as arsenic is deposited by about 300 nm, thereby completely filling the trench 105.
Next, as shown in FIG. 20B, third polysilicon 110 is buried. More specifically, an etch back process using CMP and RIE is performed to etch the polysilicon 109 to a depth of 0.25 μm from the silicon surface. The exposed collar silicon oxide film 108 is etched away, and third polysilicon 110 doped with an n-type impurity such as arsenic is deposited by about 200 nm, thereby completely filling the trench 105.
Finally, as shown in FIG. 20C, an etch back process using CMP and RIE is performed to etch the polysilicon 110 to a depth of 0.05 μm from the surface of the silicon substrate 101. After that, the upper surface of the trench 105 is covered with a silicon oxide film 111, and the silicon nitride film 103 is removed to complete a trench capacitor buried in the silicon substrate.
As an electrical connection terminal to this trench capacitor, an n-type diffusion layer 112 formed by an n-type impurity such as arsenic oozing out from the third polysilicon 110 is used.
Unfortunately, this trench capacitor relevant to the present invention has the problem that read and write operations are difficult to perform at high speed. That is, This trench capacitor is formed by filling the 5-μm deep trench with the polysilicon portions 107, 109, and 110. Although each of these polysilicon portions is doped with an n-type impurity such as arsenic, the electrical sheet resistance is very high, about a few kΩ. This prolongs the time of signal propagation by CR delay, so the read/write time cannot be shortened.
Meanwhile, with the advance of information communication technologies, demands for high-speed, large-capacity DRAMs are more and more increasing. The latest 256-M versatile DRAM and a DRAM-embedded logic device formed by the 0.18-μm rule use the above-mentioned trench capacitor structure. However, the operating speed is limited for the above reason.
Also, these devices must be improved in many respects from the viewpoint of integration density. That is, these devices relevant to the present invention use a “folded bit line system” in order to reduce the cell area. To further advance micropatterning and high integration, it is necessary to, e.g., {circle around (1)} shorten the gate length of a cell transistor, {circle around (2)} use a self-aligned contact structure as a bit line contact, and {circle around (3)} use a newly designed cell.
Furthermore, in present DRAM/logic embedded devices, salicide is adhered to the gate in order to improve the data transfer rate of the DRAM. To further improve this data transfer rate, it is necessary to develop a novel capacitor structure having a lower resistance and to also develop a gate electrode structure matching well with this novel capacitor structure.